General
Description
The PB8051 is a 8031 implementation of the popular 8051 Microcontroller Family.
Iincludes the two timers and serial port found in the 8031. PB8051 is fully
software compatible with a 8031, able to execute object code generated by 8051
design tools. Program code may be executed from an FPGA internal Block RAM(ROM)
or external (to FPGA) EPROM. The core is not clock cycle execution compatible
with the native microcontroller.
Functional
Description
The PB8051 is emulated using the Xilinx PicoBaze softcore microcontroller.
This architecture optimizes for small core size, only 28% the size of competing
8051 cores. The performance speed is similar to that of 8051when operated at
4X the clock rate. In other words, a PB8051 operated at 48 MHz will perform
similar to an legacy 8051 running at 12 MHz. The functional block diagram for
the PB8051 is illustrated in figure 1. The heart of the core is the PicoBlaze
softcore processor and it emulation program stored in a 1K x 16 block ROM.
The PicoBlaze allows for a 256 byte peripheral bus that provides access to
the serial port, timers, emulation peripherals, and block RAM. Access to this
bus remains internal to the PB8051. |
AllianceCORE™ Facts
|
Provided
with Core
|
| Documentation |
User/Design
guide
|
| Design
File Formats |
EDIF
netlist
|
| Constraints
Files |
PB8051.ucf
|
| Verification |
Test
bench & 8051 test code
|
| Instantiation
templates |
VHDL,
Verilog
|
| Reference
designs & application notes |
Design
examples witn external bus interface & test software
|
| Additional
Items |
Custom
versions of 8051 core
|
Simulation
Tool Used
|
ModelSim
and Aldec Active HDL
|
Support
|
Support
provided by Roman-Jones, Inc.
|
|
Instruction Emulation
Execution of 8031 program code is not clock cycle compatible with
the native 8031 since each instruction is emulated in PicoBlaze
software. Some instruction emulation is more efficient than others.
Instruction execution times in clock cycles is provided.
Memory & Peripheral
Interface
To accomade slower off FPGA memory and peripherals output signals
INSTR_FETCH and EXT_BUS_START indicate start of 8031 bus cycles.
These signals can interface to a bus controller to extend access
time via the input signal EXT_BUS_HOLD. A reference design
is provided.
Timer & Serial
Clocking
Separate clock enable signals are provided for 8031 timer prescale
and serial mode 0 and mode 2 prescale. These provide user flexibility
in providing counting and baud rates. These clock prescale
enables are periodic, one clock wide, and syncornous to the
system CLK input.
8051 Reset
While the RST input resets the entire core, it is not necessary
and may be tied to gnd. RST_8051 is an emulated reset that
performs the same function as the 8031 reset input.
Core Modifications
The design of the PB8051 is organized as an 8051 core with timers
and serial port. While the PB8051 is not user configurable,
Roman-Jones, Inc. is available to custom build a 8051 derivative
to meet your needs.
Core I/O Signals
The core signal I/O have not been fixed to specific device pins
to provide flexibility for interfacing with user logic. Any
signals may be used internal or external to the FPGA. Descriptions
of all signal I/O are provided below.
|
Verification
Methods
A reference design including a VHDL/Verilog Testbench and 8051 hex
and assembler source code are provided. The testbench simulates virtual
execution of 8051 assembled code from an intel hex file (assmebler
tool output). This flexibility allows users to quickly integrate
their FPGA RTL with the PB8051 core and use their own 8051 code.
Reference Design
The PB8051 includes a reference top level design that instatiantes
the PB8051 core. This reference design assumes a 44.236 MHz (chosen
for serial baud rate) clock input. The design correctly sets
the timer and serial prescales and interfaces with an external
27C512 EPROM for code storage. An offchip external 8031 bus is
provided along with ports P1 and P3. The design illustrates proper
use to extend bus cycles for the 27C512 and slow peripherials.
Recommended Design Experience
The PB8051 core is designed for ease of use. Designer should be
experienced in instantiating cores. Maybe an aggressive first
Xilinx design experience, but very simple for someone with Xilinx
tool experienced. Users should be familiar with 8051 micorcoltrollers,
skilled with assembler and/or “C” language, and related
software development tools.
Product Support
The PB8051 core is priced low at $495 including the two versions
of the core, reference deisgn, simulation testbench, and documentation.
Support is provided on an hourly basis additional cost via telephone,
email, and onsite (if requested).
Ordering Information
This AllianceCORE product is available online via credit card from
Roman-Jones, Inc. under the terms
of the
SignOnce IP License.
To learn about the SignOnce IP License program, contact Roman-Jones,
Inc. or visit www.xilinx.com/ipcenter/signonce.htm or
write to commonlicense@xilinx.com.
When you order the PB8051, a SignOnce IP License will be emailed
to you for signing. Once the signed agreement has been recieved,
the PB8051 core application package will be emailed to you.
|
Core
I/O Signals
| Signal |
Signal
Direction |
Description |
| CLK |
input |
Clock
input |
| RST |
input |
Core
reset |
| RST_8051 |
input |
8051
reset emulation |
| TIMER_PRE |
input |
Clock
enable for timers, see text |
| SERIAL0_PRE12 |
input |
Clock
enable for serial mode 0, see text |
| SERIAL2_PRE32 |
input |
Clock
enable for serial mode 2, see text |
| WR |
output |
External
write enable, high for one clock |
| RD |
output |
External
read enable, high for one clock |
| PSEN |
output |
Instruction
read enable, high for one clock |
| EXT_BUS_HOLD |
input |
Hold
line for access to slow memory or peripherals |
| INSTR_FETCH |
output |
Indicates
start fo instruction fetch cycle, high for one clock |
| EXT_BUS_START |
output |
Indicates
start fo external bus cycle, high for one clock |
| P1_IN[7:0] |
input |
Port
1 data in |
| P1_OUT[7:0] |
output |
Port
1 data out |
| P3_IN[5:0] |
input |
Port
3 data in |
| P3_OUT[5:0] |
output |
Port
3 data out |
| EXT_DATA_IN[7:0] |
input |
External
bus data in (port 0) |
| EXT_DATA_OUT[7:0] |
output |
External
bus data out (port 0) |
| EXT_ADDRESS[15:0] |
output |
External
bus address out (ports 0 and 2) |
| ROM_DATA[7:0] |
input |
Code
space data in (port 0) |
| ROM_ADDRESS[15:0] |
output |
Code
space address out (ports 0 and 2) |
|
